1. Field of the Invention
The present invention relates to the structure of interconnect-wires in a semiconductor device. More specifically, the invention relates to improvements in the interconnection pattern and structure of fuse interconnect-wires in an LSI chip.
2. Description of the Related Art
Semiconductor devices are generally known, which have a redundancy circuit for disabling defects components, if any. Most redundancy circuits have fuse interconnect-wires. The fuse interconnect-wires may be blown when applied with a laser beam, to disconnect the defective components from the normally functioning components.
Here, the fuse interconnect-wires and some associated components, all incorporated in a semiconductor device, for example, an LSI chip, will be described briefly with reference to FIGS. 21, 22, and 23. FIG. 21 is a sectional view of an LSI chip, taken along the width of fuse interconnect-wires. FIG. 22 is a sectional view taken along line X—X in FIG. 21, more precisely a sectional view taken in the lengthwise direction of the fuse interconnect-wires. FIG. 23 is a plan view of the LSI chip looked from above, showing the fuse interconnect-wires and the associated components.
A multi-layered interconnect-wire structure is formed on a silicon substrate 101. FIG. 21 typically illustrates two layers of interconnect-wires 102: the topmost layer and the underlying layer. Each interconnect-wire is generally formed of Cu or Al and Cu is used in this example. Pads 103a are generally formed of AlCu, Cu, or a composite. In this case, pads 103a are formed of Cu.
On the substrate 101 there are provided a plurality of interlayer insulating films 104 each of which is separated from the adjacent one by a diffusion barrier film 105. For the Cu interconnect-wires 102, each of the interlayer insulating films 104 is generally made of a plasma-deposited SiO2 film, a low-k (low relative permittivity) dielectric film, a silicon nitride film, or a composite film thereof. In this example, each interlayer insulating film is formed of plasma-deposited SiO2. For the Cu interconnect-wires 102, to prevent the diffusion of Cu, each of the diffusion barrier films 105 is generally formed of silicon nitride, silicon carbide (SiC), silicon carbonitride (SiCN), or a material having substantially the same properties as these materials. In this example, each diffusion barrier film is made of silicon nitride. The topmost interlayer insulating film 104 and the underlying Cu diffusion barrier film 105 are formed as a so-called passivation film 106.
Between each Cu interconnect-wire 102 and the SiO2 film 104 is provided a barrier metal film 107, which is a film consisting of a refractory metal such as Ta, Nb, W, or Ti, a film consisting of a nitride of one of such metals, or a composite film of refractory metal/refractory metal nitride.
With LSI chips of the multi-layered interconnect-wire structure, the Cu interconnect-wires at the second layer and any upper layer are generally formed by dual damascene process, single damascene process, or RIE process. The Cu interconnect-wires 102a and pads 103a, all provided on the uppermost layer, have been formed by dual damascene process and are integral with a via plug 108 by the dual damascene process. Thus, the Cu interconnect-wires 102a and pads 103a have so-called “dual damascene structure.”
With LSI chips of the multi-layered interconnection structure, fuse interconnect-wires are generally provided in a layer or layers below the topmost layer. For example, as shown in FIG. 21, some of the Cu interconnect-wires 102 which are located one layer below the topmost layer are used as fuse interconnect-wires 103. A so-called fuse window is provided above the Cu fuse interconnect-wires 103 in order to make it easy to disconnect a predetermined fuse interconnect-wire or wires. In order to reduce the process cost of manufacture of LSI chips, the fuse window 109 is generally formed concurrently with etching the top-level interlayer insulating film 104 to expose the pads 103a for the top-level interconnect-wires.
Since the Cu fuse interconnect-wires 103 are subject to oxidation, it is not desirable to open fully the bottom 110 of the fuse window 109 to thereby expose the surface of the Cu fuse interconnect-wires 103. In order to facilitate fuse blow, however, it is required to reduce the thickness of the SiO2 film 104 and the Cu diffusion barrier film 105 which are left over the Cu fuse interconnect-wires 103. Therefore, the fuse window 109 is formed so that the remaining film 104 between the bottom 110 and the surface of the Cu fuse interconnect-wires 103 has as small a thickness as possible.
In forming the fuse window 109, etching characteristics will make it easy for the top of the bottom 110 to be shaped into an arch-like form as shown in FIGS. 21 and 22. As a result, a so-called trenching phenomenon may occur in the periphery of the bottom 110 of the fuse window 109 by which the surface of the Cu fuse interconnect-wires 103 is partly exposed as shown in FIGS. 22 and 23. When the surface of the Cu fuse interconnect-wires 103 is partly exposed, they will be oxidized from the exposed portions. As a result, the resistance of the Cu fuse interconnect-wires 103 increases, degrading their quality. This may also cause the overall quality of the LSI chip to suffer. On the other hand, the etching characteristic makes it very difficult to improve the shape of the bottom 110 of the fuse window 109 so as not to expose the Cu interconnect-wires with the remaining film 104 over the interconnect-wires being formed small in thickness, thereby preventing oxidation of the Cu fuse interconnect-wires 103.
Etching so as not to expose the surface of the Cu fuse interconnect-wires 103 will increase the thickness of the remaining film 104 on the Cu fuse interconnect-wires 103. This will require an increase in the energy of laser beams needed to blow the fuses. Increasing the laser beam energy may damage a Cu fuse interconnect-wire adjacent to a target fuse interconnect-wire to be disconnected. This may lower the reliability of all the fuse interconnect-wires 103. To prevent this, it is required to set the spacing between adjacent fuse interconnect-wires (the fuse pitch) to a predetermined value or more. Specifically, it is required to set the fuse pitch to not less than a limiting value defined by the laser beam energy, i.e., the processing accuracy of laser beams. Thereby, it becomes possible to irradiate only a target fuse interconnect-wire or wires to be disconnected with a laser beam.
As described above, increasing the thickness of the remaining film 104 results in restrictions on the arrangement of the Cu fuse interconnect-wires 103; that is, limitations are encountered in making the pitch of the interconnect-wires finer. The limitations will reduce the number of the fuse interconnect-wires 103 to be incorporated into LSI chips. This reduces the rate at which chips are relieved through fuse blow, i.e., the manufacturing yield of LSI chips. Increasing the thickness of the remaining film 104 needs increasing the output power of laser beams or their fine processing accuracy. This may result in an increase in the process cost of LSIs.
In recent years, with microstructuring of and increasing packing density of semiconductor devices, various electronic circuits within the semiconductor devices have also been scaled down in dimensions and increased in packing density. This has accompanied an increase in the number of fuse interconnect-wires. With such a fuse interconnect-wire structure as shown in FIG. 23, in order to increase the number of the fuse interconnect-wires 103, it is required to increase the size of the fuse interconnect-wire area. As a result, the area occupied by the fuse interconnect-wire area in a semiconductor device increases, resulting in a reduction in the scale of a saving circuit that can be built into the device. For this reason, the chip saving rate may be lowered.
To increase the number of the fuse interconnect-wires 103, they are made finer rather than making the fuse interconnect-wire area larger. This will result in exposed portions of the fuse interconnect-wires becoming easy to be oxidized when the periphery of the bottom 110 of the fuse window 109 is opened. That is, LSI chips become easy to suffer deterioration in quality. When the number of the fuse interconnect-wires 103 is increased without making the fuse interconnect-wire area large, the fuse pitch may be decreased imprudently below the limit defined by the laser beam processing accuracy. This will make the fuse interconnect-wires 103 easy to be damaged by fuse blow as described above, lowering their reliability.